When placing multiple groups of device instances in a row region in a placement layout or floorplan, these multiple groups of device instances may interact with one another. In addition, these multiple groups may have some spatial or functional relations with each other while one or more of these relations may bear on, for example, individual circuit components in these multiple groups. Nonetheless, a group (e.g., a module generated by a module generation process, a fig_group in OpenAccess®, a cell created by a make cell command, a block of instances or circuit component designs selected by a designer, etc.) includes a plurality of circuit component designs whose relative locations are fixed within a group. That is, a group is often generated for a plurality of individual circuit component designs so that the group may be manipulated by electronic design automation tools as a whole, without manipulating individual circuit components therein.
Often, a designer may need to manipulate the design details within a group in a hierarchical placement layout or floorplan. For example, a designer may need to modify one or more instances located at the third hierarchy in a group that is located at the top hierarchy in a hierarchical placement layout or floorplan. Some conventional approaches require descend into the third hierarchy so that EDA (electronic design automation) tools may access these one or more instances at the third hierarchy while design data located at the fourth or lower hierarchies may not be accessed or even exposed in the layout window. Although the designer may perform various operations on these one or more instances at the third hierarchy, the designer does so without regard instances at higher hierarchies—the top hierarchy and the second hierarchy above the third hierarchy.
Some other conventional approaches attempt to address this shortcoming by flattening either the entire group or all the way to the third hierarchy so that the design details at and above the third hierarchy within the group is exposed. Nonetheless, these other conventional approaches still fail to provide proper context information about design details outside the group to the EDA tools while manipulating the one or more instances at the third hierarchy in the selected group of interest.
These shortcomings of conventional approaches are further exacerbated in top down approaches where the portion of an integrated circuit (IC) design at higher hierarchies are implemented before that at lower hierarchies. In such top-down approaches, higher level groups, cells, or blocks are first placed into the layout, and the details at lower hierarchies of these higher hierarchy groups, cells, or blocks are subsequently implemented. With conventional approaches descending into a specific group, the internal details of a group are thus implemented without regard to surrounding circuit component designs outside the group and thus often require several rounds of iterative implementations to implement or optimize a group of instances. That is, conventional approaches for manipulating hierarchical designs fail to provide proper context information across the boundaries of a group, cell, or block during the manipulation within the boundaries of the group, cell, or block.
Therefore, there is a need for implementing context aware placement for an electronic design to address at least the foregoing issues with conventional approaches.